1. Field of the Invention
The present invention relates to an amplification type solid-state imaging device including an array of amplification type solid-state imaging elements each having a transistor such as an MOSFET and a junction gate FET which accumulates signal charge obtained by photoelectric conversion of incident light and outputs electric signals corresponding to the accumulated signal charge.
2. Description of the Related Art
A charge-coupled device (CCD) type solid-state imaging device has been widely used in various fields as a featuring device of a solid-state imaging device. In a CCD type imaging device, signal charge, which is photoelectrically-converted and accumulated by a photodiode or a MOS diode, are transferred via a CCD transfer channel to a high-sensitivity charge detection portion and converted there into voltage signals. As a result, the CCD type imaging device has a higher signal-to-noise (S/N) ratio and a larger output voltage.
However, in order to meet the demand that such an imaging device should be smaller-sized and have a larger number of pixels, the size of a pixel to be used should be smaller and the amount of charge that can be transferred by a CCD should be reduced. Consequently, there have occurred serious problems such as a scale-down of the dynamic range, a significant increase of the power consumption, and the like. Because a larger amount of load capacitance and a higher driving voltage are required to drive the entire CCD device by several phases of clocks, the power consumption sharply increases as a larger number of pixels are used.
In order to overcome the above problems, an amplification type solid-state imaging device has been proposed, where signal charge generated in each pixel is not directly read, but a signal is first amplified in each pixel and read via a scanning circuit. By amplifying the signal in each pixel, the signal is no more limited, providing a wider dynamic range than the CCD type device. Moreover, only a horizontal line and a vertical line corresponding to a selected pixel from which a signal is to be read can be driven, and the required driving voltage is low. This reduces the power consumption compared with the CCD device.
Transistors are generally used for the above signal amplification in each pixel. Among various types of transistors such as a SIT, a bipolar type transistor, and a FET (a MOSFET and a junction type FET), a FET is advantageously used in consideration of the construction of the entire device since it is easy in construction to use a MOSFET for a scanning circuit for signal readout. (While a SIT and a bipolar type transistor are formed in the depth direction, a FET is formed in the plane direction, which facilitates the fabrication of the transistor).
FIG. 11A is a partial plan view of an amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called twin gate MOS image sensor (TGMIS) type. This type of the element has been proposed in Japanese Patent Application No. 6-303953 by the Applicant of the present application, which was published as Japanese Laid-Open Patent Publication No. 8-78653 on Mar. 22, 1996. FIG. 11B is a sectional view taken along line A-A' of FIG. 11A.
Referring to FIG. 11B, first gate electrodes 2 and second gate electrodes 3 are formed on a p-type semiconductor substrate 1 via an insulating film. Well layers 4 are formed in regions of the surface area of the semiconductor substrate 1 located directly under the first gate electrodes 2. Source regions 5 and drain regions 6 made of n+ diffusion layers are formed in the surface areas of the well layers 4 to constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate.
Referring to FIG. 1A, each first gate electrode 2 surrounds the source region 5 of each MOS type transistor, forming a pixel. Such pixels are arranged in the horizontal and vertical directions. The first gate electrodes 2 of horizontally adjacent pixels are connected to each other via horizontal connecting sections 2a. The second gate electrodes 3 are formed directly under the horizontal connecting sections 2a. Each drain region 6 surrounds the first gate electrode 2 and the second gate electrode 3 of each pixel.
Drain terminals VD are connected to the drain regions 6, while signal read terminals VS are connected to the source regions 5 via signal lines (column lines) connected to respective columns of pixels aligned in the vertical direction. Control terminals VGA are connected to the first gate electrodes 2, while control terminals VGB are connected to the second gate electrodes 3.
With the above configuration, a light energy h.nu. incident via each first gate electrode 2 causes pairs of electrons and holes to be generated in the transistor by photoelectric conversion. While electrons flow into the drain region 6, holes are confined by a barrier formed in the middle of the n-type well layer and a barrier formed under the second gate electrode 3 to become signal charge accumulated at the semiconductor/insulating film interface of the n-type well layer 4. The potential in the n-type well layer 4 changes depending on the amount of the accumulated signal charge. The amount of this change in the potential is read via the signal read terminal VS as a change in the source potential and output as a pixel signal.
The signal charge is drained in a reset operation after the above signal read operation. This can be easily achieved by lowering the potential barrier under the second gate electrode 3 to allow the accumulated signal charge to flow transversely toward the region located under the second gate electrode 3 and then vertically toward the p-type semiconductor substrate 1 as shown by an arrow 7 in FIG. 11B.
FIG. 12A is a partial plan view of another amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called surface reset type obtained by improving the above TGMIS type. This type of imaging element has been proposed in Japanese Patent Application No. 8-19199 by the Applicant of the present application. FIG. 12B is a sectional view taken along line A-A' of FIG. 12A.
Referring to FIGS. 12A and 12B, n-type semiconductor well layers 4 are formed in the surface area of a p-type semiconductor substrate 1. First gate electrodes 2 which are to be part of first gate regions are formed on the n-type semiconductor well layers 4, while second gate electrodes 3 which are to be part of second gate regions are formed on the exposed portions of the p-type semiconductor 1 located adjacent to the n-type semiconductor well layers 4. P-type low-resistance surface reset drains 8 are formed in the second gate regions between the adjacent n-type semiconductor well layers 4 before the formation of the second gate electrodes 3, to secure regions where potential barriers are formed by the second gate electrodes 3. Thereafter, n.sup.+ -type diffusion layers are formed for sources 5 and drains 6 which constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate. The reset drains 8 are formed in the surface area of the semiconductor substrate 1 under the second gate electrodes 3.
With the above configuration, a light energy h.nu. incident via each first gate electrode 2 causes pairs of electrons and holes to be generated in a photoelectric conversion region of the n-type semiconductor well layer 4 by photoelectric conversion. While electrons flow into the drain region, holes are confined by a barrier formed in the middle of the n-type semiconductor well layer 4 and a barrier formed under the second gate electrode 3 to become signal charge accumulated at the semiconductor/insulating film interface of the first gate region. The potential in the n-type semiconductor well layer 4 changes depending on the amount of the accumulated signal charge. The amount of this change in the potential is read as a potential change in the source 5 and output as a pixel signal.
The signal charge is easily drained in the reset operation by lowering the potential barrier under the second gate electrode 3 to allow the accumulated signal charge to flow into the reset drain 8 via a route shown by an arrow 7 in FIG. 12B. In this imaging device, the accumulated charge can be completely drained without influence of a potential ridge 107 formed in the middle between the semiconductor surface of the second gate region and the p-type semiconductor substrate 1. As for the potential ridge 107, refer to the aforementioned patent application.
Referring to FIG. 12A, each first gate electrode 2 surrounds the source region 5 of each MOS type transistor, forming a pixel. Such pixels are arranged in the horizontal and vertical directions, and the first gate electrodes 2 of horizontally adjacent pixels are connected to each other via horizontal connecting sections 2a. The second gate electrodes 3 are formed directly under the horizontal connecting sections 2a. Each drain region 6 surrounds the first gate electrode 2 and the second gate electrode 3 of each pixel.
Drain terminals VD are connected to the drain regions 6, while signal read terminals VS are connected to the source regions 5 via signal lines (column lines) connected to respective columns of pixels aligned in the vertical direction. Control terminals VGA are connected to the first gate electrodes 2, while control terminals VGB are connected to the second gate electrodes 3.
FIG. 13A is a partial plan view of yet another amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called trench type obtained by improving the above TGMIS type from another aspect. This type of imaging element has been disclosed in Japanese Patent Application No. 8-19200 by the Applicant of the present application. The configuration of this amplification type solid-state imaging device is the same as those shown in FIGS. 11A and 12A except for the formation of a trench structure in a portion between each second gate region and the adjacent drain region, and thus detailed description thereof is omitted. FIG. 13B is a sectional view taken along line A-A' of FIG. 13A.
Referring to FIGS. 13A and 13B, n-type semiconductor well layers 4 are formed in the surface area of a p-type semiconductor substrate 1. First gate electrodes 2 which are to be part of first gate regions are formed on the n-type semiconductor well layers 4, while second gate electrodes 3 which are to be part of second gate regions are formed on the exposed portions of the p-type semiconductor 1 located adjacent to the n-type semiconductor well layers 4. Then, n.sup.+ -type diffusion layers are formed for sources 5 and drains 6 which constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate.
The TGMIS type amplification type solid-state imaging device shown in FIGS. 11A and 11B has a problem such that, as the width of the second gate electrode becomes smaller with the reduction of the pixel size, a three-dimensional potential ridge is formed on a route for the drainage of the accumulated charge due to the potential applied to the source and the drain. This potential ridge prevents the accumulated charge from being completely drained into the semiconductor substrate.
In the trench-type device, a trench structure 9 is formed adjacent to the second gate region to suppress the formation of such a potential ridge. This makes it possible to spatially lower the potential applied to the source 5 and the drain 6 and thus secure a channel through which the accumulated charge flows into the semiconductor substrate 1.
The trench structure is not necessarily formed over the entire region adjacent to the second gate region, but may be formed only over a portion of the region since the accumulated charge can be completely drained by securing such a portion formed as a reset drain under the second gate region.
In the reset operation, a high voltage VGA(H) which is, for example, the same as that applied when signal charge is accumulated, is previously applied to the first gate electrode 2. An intermediate voltage VGA(M) which is, for example, the same as that applied when signal charge is accumulated, is applied to the second gate electrode 3. At this time, the surface potential under the second gate electrode 3 is sufficiently lower than the surface potential of the n-type semiconductor well layer 4 obtained when no signal exists. This allows all signal charge (holes) in the surface area of the n-type semiconductor well layer 4 to flow into the p-type semiconductor substrate 1 through the potential barrier gate under the second gate electrode 3. In other words, the reset operation is effected.
At this time, thanks to the existence of the trench structure 9, there is formed no potential ridge which tends to be formed in the middle of the region under the second gate electrode 3 preventing the accumulated charge from being drained.
FIG. 14A is a plan view of yet another application type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called bulk drain MOS image sensor (BDMIS) type. This type of imaging element has been disclosed in Japanese Patent Application No. 7-51641 by the Applicant of the present application. FIG. 14B is a part of a sectional view taken along line A-A' of FIG. 14A.
Referring to FIG. 14B, n-type wells 4 are formed in the surface area of a p-type semiconductor substrate 1 so that the surface thereof is on the same level as a principal surface 11 of the p-type semiconductor substrate 1. A p.sup.+ -type semiconductor region 5 is formed in the surface area of each well 4 so that the surface thereof is on the same level as the principal surface 11. A first gate electrode 2 is formed on the well 4 excluding the area where the semiconductor region 5 is formed via an insulating film. A second gate electrode 3 is formed on the exposed surface of the semiconductor substrate 1 adjacent to the well 4 via the insulating film. The surface area of the well 4, the insulating film, and the first gate electrode 2 constitute a first gate region. Likewise, the exposed surface area of the semiconductor substrate 1, the insulating film, and the second gate electrode 3 constitute a second gate region.
When an appropriate voltage is applied to the first gate electrode 2, a p-channel is formed in the surface area of the first gate region for the flow of holes which are minor carriers. When an appropriate voltage is applied to the second gate electrode 3, the entire portion of the semiconductor substrate 1 located under the second gate electrode 3 as well as the surface area of the second gate region form a p-channel. Under the above conditions, when a voltage V.sub.D is applied to the semiconductor substrate 1 and a voltage V.sub.S is applied to the semiconductor region 5, a channel for flowing holes is formed between the semiconductor substrate 1 and the semiconductor region 5. A current thus flows through this channel as shown by a solid-line arrow in FIG. 14B.
With the above configuration, a light energy h.nu. incident via the first gate electrode 2 causes pairs of electrons and holes to be generated in the portions of the well 4 and the semiconductor substrate 1 located under the first gate electrode 2 by photoelectric conversion. The holes flow into the semiconductor region, while the electrons are accumulated in a potential well formed in the middle of the well 4 as signal charge. The electrons used as the signal charge are major carriers in the well 4. The potential at the well 4 and thus the potential at the surface area of the first gate region change depending on the amount of the accumulated signal charge.
Consequently, the current flowing between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of the accumulated signal charge. Thus, by keeping a predetermined current flow between the semiconductor substrate 1 and the semiconductor region 5, the potential between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of accumulated signal charge. By keeping a predetermined potential between the semiconductor substrate 1 and the semiconductor region 5, however, the current flowing between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of accumulated signal charge. In this way, a first active element is formed between the semiconductor substrate 1 and the semiconductor region 5 having a channel composed of the surface areas of the first gate region and the second gate region. The electric characteristics of this active element change depending on the amount of accumulated signal charge.
A reset drain region 10 is also formed at the surface area of the semiconductor substrate 1 so that the surface thereof is on the same level as the principal surface 11. The reset drain region 10 is in contact with the surface area of the second gate region on the side opposite to the first gate region. An appropriate voltage is applied to the second gate electrode 3 to lower the potential barrier in the surface area of the second gate region. Then, the signal charge accumulated in the well 4 flows into the reset drain region 10 via a route shown by a dotted-line arrow in FIG. 14B. In this way, a second active element is formed between the well 4 and the reset drain region 10 having a channel composed of the surface area of the second gate region, realizing the drainage of the signal charge.
A plurality of amplification type solid-state imaging elements as shown in FIG. 14B are arranged in a matrix as shown in FIG. 14A. Rows of the first gate electrodes 2 aligned in the horizontal direction are commonly connected to respective clock lines VGA(i), VGA(i+1), . . . Likewise, rows of the second gate electrodes 3 aligned in the horizontal direction are commonly connected to respective clock lines VGB(i), VGB(i+1), . . .
The semiconductor region 5 which serves as a source is formed in the center of the first gate region of the well 4 of each amplification type solid-state imaging element. Columns of the semiconductor regions 5 aligned in the vertical direction are commonly connected to respective signal lines VS(j), VS(j+1), . . . The semiconductor substrate 1 itself is used as the drain of each transistor, which is therefore not shown in FIG. 14A.
FIG. 15 is a schematic view in combination of an equivalent circuit diagram and a block diagram illustrating a configuration of an amplification type solid-state imaging device using the amplification type solid-state imaging elements of the TGMIS type shown in FIGS. 11A and 11B.
Referring to FIG. 15, amplification type solid-state imaging elements (pixels) 11-11, 11-12, . . . 11-1n, 11-21, . . . , 11-mn are arranged in a horizontal (X) direction and a vertical (Y) direction to form a matrix. Terminals of the first gate electrodes 2 of rows of the amplification type solid-state imaging elements aligned in the X direction are connected to a first vertical scanning circuit 13 via respective first scanning lines 12-1, 12-2, . . . , 12-m. Terminals of the second gate electrodes 3 of rows of the amplification type solid-state imaging elements aligned in the X direction are connected to a second vertical scanning circuit 15 via respective second scanning lines 14-1, 14-2, . . . , 14-m. The signal read operation and the reset operation are conducted for each horizontal row of pixels by sequentially selecting each horizontal row of pixels via the first and second vertical scanning circuits 13 and 15.
Terminals of source regions 5 of columns of the amplification type solid-state imaging elements aligned in the Y direction are connected to respective column lines 16-1, 16-2, . . . , 16-n. The column lines 16-1, 16-2, . . . , 16-n are commonly connected to a video line 18 via respective column selective transistors 17-1, 17-2, . . . , 17-n. The video line 18 is grounded via a fixed current source load 19 while being connected to a signal output terminal 20. Control terminals of the column selective transistors 17-1, 17-2, . . . , 17-n are connected to a horizontal scanning circuit 21 so that the respective column selective transistors 17-1, 17-2, . . . , 17-n are sequentially selected and driven based on a control signal sent from the horizontal scanning circuit 21. The drain regions 6 of the amplification type solid-state imaging elements 11-11 to 11-mn are commonly connected, and a predetermined voltage is applied to the drain regions 6.
Thus, the above amplification type solid-state imaging device adopts a source/gate selection method, where columns of the pixels 11-11 to 11-mn are sequentially selected for each selection of a row of the pixels, and output signals of the respective selected pixels are sequentially read from the signal output terminal 20 via the video line 18.
The operation of the above solid-state imaging device will be described with reference to FIG. 16.
FIG. 16 is a timing chart showing the waveforms of signals used in the amplification type solid-state imaging device. The first vertical scanning circuit 13 outputs a first scanning pulse .phi.GI.sub.i to an i-th first scanning line 12-i. The second vertical scanning circuit 15 outputs a second scanning pulse .phi.GII.sub.i to an i-th second scanning line 14-i. The horizontal scanning circuit 21 outputs a signal read control pulse .phi.S.sub.j to a j-th column line 16-j.
First, the first vertical scanning circuit 13 sequentially outputs first scanning pulses (.phi.GI.sub.1, .phi.GI.sub.2, . . . , .phi.GI.sub.m of a low level VG(L) or a high level VG(H) in this order to the first gate electrodes 2 of the respective horizontal rows of pixels via the corresponding first scanning lines 12-1, 12-2, . . . , 12-m. Simultaneously, the second vertical scanning circuit 15 sequentially outputs second scanning pulses .phi.GII.sub.1, .phi.GII.sub.2, . . . , .phi.GII.sub.m of a low level VRG(L) or a high level VRG(H) in this order to the second gate electrodes 3 of the respective horizontal rows of pixels via the corresponding second scanning lines 14-1, 14-2, . . . , 14-m. At this time, the combination of the VG(H) of the first scanning pulse .phi.GI.sub.i and the VRG(H) of the second scanning pulse .phi.GII.sub.i is set in a signal read scanning period .tau.H for an i-th horizontal row of pixels. The combination of the VG(H) of a first scanning pulse .phi.GI.sub.(i+1) and the VRG(L) of a second scanning pulse .phi.GII.sub.(i+1) is set in a blanking period .tau.BL which starts from the end of the scanning of the i-th horizontal row of pixels and ends at the start of the scanning of the next (i+1)th row of pixels.
During the signal read scanning period .tau.H for the i-th row of pixels, the column selective transistors 17-1 17-2, . . . , 17-n are sequentially turned on with the signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n output from the horizontal scanning circuit 21. With this sequential activation of the column selective transistors, pixel signals which have been read from the amplification type solid-state imaging elements onto the corresponding column lines 16-1, 16-2, . . . , 16-n are sequentially read onto the video line 18. The signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n as the horizontal scanning signals supplied to the gate terminals of the column selective transistors 17-1, 17-2, . . . , 17-n are signals for sequentially selecting the column lines. The voltage values of these signals are set so that, when the signal level is low, a transistor among the column selective transistors 17-1, 17-2, . . . , 17-n which has received the low-level voltage is turned off, while, when the signal level is high, a transistor which has received the high-level voltage is turned on.
The i-th horizontal row of the amplification type solid-sate imaging elements are all reset at a time when the first scanning pulse .phi.GI.sub.i becomes the high level VG(H) and the second scanning pulse .phi.GII.sub.i becomes the low level VRG(L). This reset operation is conducted during the blanking period .tau.BL.
In this way, pixel signals are sequentially read from each horizontal row of pixels to obtain a field of video signals, and then reset.
Hereinbelow, the signal read operation and the reset operation for the first horizontal row of pixels will be described as an example.
Referring to FIG. 16, when the first scanning pulse .phi.GI.sub.1 output from the first vertical scanning circuit 13 becomes the high level VG(H) and the second scanning pulse .phi.GII.sub.1 output from the second vertical scanning circuit 15 becomes the high level VRG(H), the first row of the amplification type solid-state imaging devices 11-11, 11-12, . . . , 11-1n connected to the first scanning line 12-1 and the second scanning line 14-1 are selected to allow the pixel signals of the first row of the pixels to be read onto the column lines 16-1, 16-2, . . . , 16-n. As the column selective transistors 17-1, 17-2, . . . , 17-n are sequentially turned on in this order with the signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n output from the horizontal scanning circuit 21, the pixel signals on the column lines 16-1, 16-2, . . . , 16-n are sequentially output from the signal output terminal 20 of the video line 18 via the column selective transistors 17-1, 17-2, . . . , 17-n. The first row of the amplification type solid-state imaging elements are then all reset at a time when the first scanning pulse .phi.GI.sub.1 keeps the high level VG(H) and the second scanning pulse .phi.GII.sub.1 becomes the low level VRG(L). The above signal read operation and the reset operation are repeated for the second and subsequent rows of pixels until one field of video signals are obtained.
According to the above amplification type solid-state imaging device, a potential change corresponding to the amount of signal charge generated by photoelectric conversion in the region under the first gate electrode 2 of each amplification type solid-state imaging element is read onto the corresponding column line 16 as a source potential. The source potential is kept unchanged and fixed as a pixel signal by charging parasitic capacitances on the column line 16 and the video line 18 by the fixed current source load 19, and output to the video line 18 via the corresponding column selective transistor 17. Since the capacitance of each amplification type solid-state imaging element is small, in order to output the exact potential at the region under the first gate electrode 2 to the column line 16 as a pixel signal, the current supplied from the constant current source load 19 should be as small as about 100 nA or less. In other words, if the current supplied from the constant current source load 19 is large, the parasitic capacitances on the column line 16 and the video line 18 are sufficiently charged, preventing delay in signal readout. However, this increases the potential at the region under the first gate electrode 2, preventing the exact potential from being output onto the column line 16 as a pixel signal. Conversely, if the current supplied from the constant current source load 19 is too small, the parasitic capacitances on the column line 16 and the video line 18 are not sufficiently charged. This dulls the signal waveform by the time constant of the parasitic capacitances, causing delay in signal readout.
In the above amplification type solid-state imaging device, only the constant current source load 19 connected to the video line 18 is provided to cover all the amplification type solid-state imaging elements formed in a matrix. This is insufficient in supplying charge to the parasitic capacitances of all the column lines 16 and the video line 18, degrading the video signal read response. Moreover, if an electric circuit is intended to be connected downstream of the video line 18, it is less likely for the video signals obtained from the amplification type solid-state imaging elements to be output at high speed.
The amplification type solid-state imaging device using the amplification type solid-state imaging elements of the TGMIS type was described hereinbefore. The same problems as those described above also arise when the solid-state imaging elements of the surface reset type, the trench type, and the BDMIS type are used instead of the TGMIS type.